MLIR-to-RTL Simulation Flow: From linalg.matmul to a Systolic Array

Introduction Hi! I'd like to share the MVP of my hw-mlir-lab project, where I use MLIR to lower matrix multiplication ( matmul ) to a systolic array simulated in Verilator. 1.

Source: [Dev.to](https://dev.to/dima365/mlir-to-rtl-simulation-flow-from-linalgmatmul-to-a-systolic-array-1gme)